Through unvarying innovation, we`re poised to provide the best IC products and services to matchup current and future ineluctably for entertainment, communication and information. Join us, as we billow ahead with the vision to enhance and enrich the lives of all.
DESIGN VERIFICATION ENGINEER
Responsibilities
- Perform Constrained- Random verification using system verilog
- Develop verification environment for DUT
- Write and debug tests for DUT using System verilog. Perl and C
- Develop Bus Functional Model [BFM] or use Verification IP [VIP] for tests
- Develop and review test plans
- Write coverage monitors to evaluate the coverage of DUT
- Bachelor`s/Masters Degree in Electrical/Electronics/Computer Engineering
- Experience in SystemVerilog/VMM/DVM/UVM [UVM is a plus]
- Familiarity with transaction level verification at higher level of abstractions is a plus
- Experience in formal verification using SystemVerilog Assortion to verify SOC or IP is a plus
- Experience in developing measurable verification plan
- Proficiency in UNIX scripting languages and utilities such as csh,sed,awk and Perl
PHYSICAL DESIGN ENGINEER
Responsibilities
- Fully responsible for Netist to GDS physical design implementation of low power chips
Requirements
- Bachelor`s/Masters Degree in Electrical/Computer Engineering
- Experience in physical design with tape outs
- Knowledge of computer netist to gds/low, including floor planning power grid synthesis,place opt. and routing,CT5,timing closure,signal integrity,STA and physical verification
- Knowledge of Sypnosys/Gadence tools like ICC or Encounter
- Expertise in low power design implementation or flow development
- Expertise in hierarchical design implementation is a plus
- Good in script programming with Perl,TCL/TK or of her languages
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